View PE12316_1068120.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 1/29 PE12316 features: ? functional and pincompatible with ti cf32006 / thct12316 ? three independent channels in one device ? each channel compatible with pe12016 ? available as ip-core or within plcc68 package ? interfaces three mechanisms / axes to data bus ? pulse width measurement ? frequency measurement ? cascadable 16-bit counters ? ttl compatible ? 5v and 3.3v operation ? 8 bit parallel tristatable bus ? simple read & write procedure ? high speed 20 mhz clock operation ? direction discriminators identify & measure forward/backward rotation ? separate zero pulse input new feature: ? each channel extendable to 24 bit figure 1 pinout description : the PE12316 triple incremental encoder interf ace consists of three channels each, which can independently determine the direction of di splacement of a mechanical or axis based device on two input signals from transducers in quadrature . alternatively, each channel can measure a pulse width using a known clock rate, or a frequency, by c ounting input pulses over a known time interval. it includes three 16/24-bit counters which may al so be used separately. the PE12316 may be cascaded between channels on one device or between devices to provide accuracy greater than 16/24-bits, and is designed for use in many microprocessor-based systems. 58 borrow1 nc pins should be left open and not connected to the pcb. they are reserved for future upgrades. 61 kli-klo2 a 1 10 a 2 11 cs 12 gnd 13 d0 14 d1 15 vcc 16 d2 17 d3 18 gnd 19 d4 20 d5 21 vcc 22 d6 23 d7 24 gnd 25 nc 26 44 ua13 m01 27 m11 28 m21 29 m02 30 nc 31 m12 32 nc 33 m22 34 m03 35 m13 36 m23 37 nc 38 ua11 39 nc 40 ua21 41 ua12 42 ua22 43 45 ua23 46 up1 47 down1 48 up2 49 down2 50 up3 51 down3 52 vcc 53 gnd 54 borrow3 55 carry3 56 borrow2 57 carry2 59 carry1 60 kli-klo3 9 a0 8 rd 7 we 6 a3 5 reset 4 nc 3 ua01 2 ua02 1 ua03 68 clk 67 nc 66 vcc 65 nc 64 gnd 63 ready 62 kli-klo1 PE12316 plcc68
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 2/29 PE12316 availability: the PE12316 is available as a replacement ic or netlist ip core, fully compatible with the ti cf32006 functionality. the replacement ic is packaged within the popular plcc68. the ip core can be targeted to any desired fpga/cpld or asic technology and is delivered within the according netlist format. the database has been proven in a co-emulation together with the reference part by stimulating both devices with the same inputs and observing the identical results on the outputs. ressource usage ip core: gate count for asic technologies is approximately 7000 gates. for fpgas a technology with at least 20.000 fpga gates like xcs20 from xilinx needs to be chosen. enhancements over cf32006: the PE12316 has 3 counters with 24 bit internally. therefore an additional addressline /a3 is introduced on pin 6 to select the bits 16- 23 of each channel in conjunction with the other addressbits a0-a2. note: if /a3 is left unconnected, PE12316 is identical to cf32006. differences: the PE12316 has some slight changes: ua1x and ua2x are synchronized with the clock, eliminating the need to place a discrete act74 type flipflop in front of these signals. due to this feature a latency of one clock cycle is introduced, resulting worst case in a +/-1 counter difference.
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 3/29 PE12316 applications: the PE12316 enables mechanical devices to be interfaced with microprocessors. it may be used in many diverse applications, including robotics, tooling machines, elevators, conveyor belts and transport mechanisms. since it contains three channels each PE12316 can support three measurements or axes of motion. architecture: within each channel there are four main elements: 1. the measurement and mode control logic generates up or down count pulses, internal signals i1 and i2, from: - quadrature signals ua1, ua2 and zero pulse ua0n* - clock input - mode controls m0n*, m1n* and m2n* 2. a 16-bit counter made up from two independently loadable 8-bit counters. 3. a 16-bit latch which ?freezes? the counter value when required. 4. a multiplexer that allows the processor to read either upper or lower byte in the latch. supporting the three channels: the control logic provides common micro- processor interface signals; the output multiplexer allows the pr ocessor to select data from one of the three channels and the three- state buffers place this data on the bus. * the suffix n is a placeholder for either channel 1, channel 2 or channel 3 and will be used in this manner throughout the whole document.
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 4/29 PE12316 figure 2 block diagramm for 16 bit mode
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 5/29 PE12316 operation: the eight modes of operation of the PE12316 are summarized in table 1 . the modes of the three channels can be selected independently. mode m2n m1n m0n mode description 0 0 0 0 counter 16-bit up/down counter (inhibits direction discriminator) direction discriminator 1 0 0 1 single count pulse synchronous with ua1n rising in forward direction and ua1n falling in backward direction. 2 0 1 0 single count pulse synchronous with ua2n rising in forward direction and ua2n falling in backward direction. 3 0 1 1 double count pulse synchronous with ua1n rising and falling. 4 1 0 0 double count pulse synchronous with ua2n rising and falling. 5 1 0 1 quadruple count pulse synchronous with all edges. 6 1 1 0 pulse width measurement ua1n is the gate signal ua2n is high for up counting and low for down counting. count is synchronous with rising clock. 7 1 1 1 frequency measurement ua1n is frequency signal to be measured ua2n is the gate signal of known time interval. count is synchronous with rising edge of ua1n. table 1 mode description
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 6/29 PE12316 detailed information about the different modes: mode 0: 16-bit up/down counter mode in this mode the PE12316 may be used as three fast 16-bit synchronous up/down counters with cascade capability. this is operated using the /up and /down inputs. the states of the counte r outputs are transferred to a 16-bit latch. the contents of this 16-bit latch are multiplexed on a 8-bit parallel data bus (d0?d7) and enabled using /rd and /cs. /a0 is the control input for the byte multiplexer. a high level at this input transfers the least significant byte to the data outputs; and a low level transfers the most significant byte. the signals /a1 and /a2 select the channel for read or write according to the following table. channel number /a1 /a2 1 h h 2 l h 3 h l no channel selected 1 l l table 2 channel selection 1 output buffers still selected if /rd and /c s active ? data bus carries invalid data the up/down counters are loaded in individual 8- bit bytes by the /wr and /cs signals, with the byte selected by the /a0 input, and the channel by the /a1 and /a2 inputs. the counters and the control logic may be cleared all together us ing the /reset signal. the counters are cleared individually using the /ua0n signals. cascading to 32, 40, 48 or 56 bits is possible by connecting the /carry, /borrow outputs of channel n with the /up, /down inputs of the channel n+1. in cascaded mode the according /kli-klon have to be connected together. for further details see application notes . memory map: /a3 /a2 /a1 /a0 channel content 1* bits 0-7 1* bits 8-15 0 1 1 1 0 1 channel 1 bits 16-23 1* bits 0-7 1* bits 8-15 0 1 0 1 0 1 channel 2 bits 16-23 1* bits 0-7 1* bits 8-15 0 0 1 1 0 1 channel 3 bits 16-23 * defaultvalue due to internal pullup table 3 memory map
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 7/29 PE12316 mode 1-5: direction discriminator modes the quadrature signals ua1n and ua2n, identify forward or backward directions. if ua1n leads ua2n, the forward direction is indicated and the counter will count up; if ua1n lags ua2n, the reverse direction is indicated and the counter will count down. figure 3 direction discriminator modes ua1n and ua2n are both stored in the first of a pair of consecutive d-type flip-flops on the clock falling edge, and transferred to the next on the clock rising edge. by comparing the states of the four flip-flops and checking the mode inputs, the up or down count pulses are generated; see figure 4 and figure 5 . figure 4 direction discriminator up clock
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 8/29 PE12316 transducer of resolution speed shaft f _ _ _ = figure 5 direction discriminator down clock modes 1 to 5 define which edge of the quadrature signals will be counted in accordance with table 1 . the clock frequency should be at least four times greater than the frequencies of the quadrature signals. this will eliminate problems resulting from timing jitter in the transducer signals a nd will allow the quadruple counting mode to be used. the frequency of the quadrature signals, ua1n and ua2n may be calculated from the relationship:
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 9/29 PE12316 mode 6: pulse width measurement mode in this mode, ua1n acts as a gate, and is the pulse width to be measured. synchronised with the clock edge after a low to high transition in ua1n, counting begins at the input clock frequency. similarly, synchronised with the clock edge after a high to low transition of ua1n, counting is disabled; the value in the counter is loaded in the output register; /kli-klon is pulled low; and then the counter clears. see figure 6 . if ua2n is held high, the counter will count up, and if ua2n is held low, the counter will count down. each counter can be preloaded in two or three bytes depending on 16 bit or 24 bit mode by activating /cs, and /we, and selecting the required byte with /a0 and /a3, and the required channel with /a1 and /a2. this must be done while ua1n is low. the output register should be read by activating /cs, /rd, and selecting the individual bytes with /a0 after ua1n has fallen and before the next preload takes place. the kli-klon signal may be used as an interrupt to indicate to the processor when the output register has been loaded. in both the pulse width and frequency modes, the output register will not be loaded via /cs and /rd, but by the falling edge of ua1n, or by pulling /kli-klon low. figure 6 pulse width measurement
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 10/29 PE12316 mode 7: frequency measurement mode in mode 7, ua1n is the signal of unknown frequency to be measured; ua2n is a gate signal of known width. a low to high transition of ua2n enables counting at the frequency of ua1n. when the gate (ua2n) goes low, counting is disabled, the value of the counter is loaded into the output register, /kli-klon is pulled low, and the counter is then cleared. see figure 7 . figure 7 frequency measurement
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 11/29 PE12316 reset operation: a total reset is initiated by pulling the /reset pin low. this will clear the counters to zero, reset the d flip-flops at the inputs of the quadrature signals (ua1n and ua2n), clear the latches that inhibit the load register pulse, and load zero into the output register. to avoid a spurious count error (+/- 1) after a reset, the ua1n and ua2n inputs should be held to the values indicated in table 4 during and just after the reset pulse. mode ua1n ua2n 0 x x 1-5 h h 6-7 l l table 4 mode selection cascading devices the /kli-klon pins of all cascaded PE12316?s should be tied together, so that all of the devices load their output registers at the same time. when the ?master? generates a pulse for the other PE12316s, /kli-klon on the ?master? works as an output, and /kli-klon on the ?slaves? work as inputs. the /carry output of one device should be tied to the /up input of the next device in the cascade. similarly, /borrow should be connected to /down. for details see figure 14 . write operation a number may be preloaded into the counter by pulling /cs and /we low while using /a0 and /a3 to direct the value on the data bus to the selected byte of the counter and /a1 & /a2 to select the required channel. this will cause /ready to go low on the next falling clock edge, and remain low until /cs and /we go high. see figure 12 . read operation when in modes 0 to 5 the contents of the counter can be read at any time by pulling /cs and /rd low. the channel is selected by using /a1 & /a2. within this channel the most significant byte may be selected by setting /a3 to low, and the least significant byte may be read by setting /a0 and /a3 high. this will cause a load output register pulse to be generated and /kli-klon will go low during the next low clock pulse. /ready will also go low as the clock goes low, and will stay low until /cs and/or /rd go high. the load output register pulse stores the current value of the counter in a 16-bit latch register and /a0 /a3 direct the selected byte through a multiplexer to the outputs : /cs and /rd also enable the 3-stat outputs ? see figure 11 . the output register will be loaded immediately if /kli- klon is pulled low externally, this signal normally comes from a cascaded device. for modes 6 & 7 see the earlier description.
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 12/29 PE12316 configuration special consideration should be paid to the automatic configurati on features of the PE12316. the purpose of these features is to allow for the different order of byte reads (high then low or low then high) of different processors when doing a word read across a byte wide bus and also to configure cascaded devices automatically for correct word read sequence ? see below. byte order configuration after a system reset has occurred, the first read operation will store the value of /a0 and /a3 in a latch within the device. from that time until the next system reset the load output register pulse during a read operation will only be generated if /a0 and /a3 are this stored value. this means that the internal load output register pulse is correctly generated for word operations regardless of the byte order of the partic ular processor. special care should be taken if reading individual bytes to ensure these operations are always done in a consistent order. cascaded configuration after a system reset the first device and channel to receive a read operation configures itself into ?master? mode and outputs a pulse on /kli-klo. in cascaded operation the /kli-klo pins of the cascaded channels are connected together and the input pulse on /kli-klo of the cascaded channels configures these to ?slave? mode. on all subsequent read operations the load output register pulse is only generated by the ?master? channel (for the appropriate polarity of /a0, as noted above) and this is fed to the ?slave? devices via the /kli-klo connection. special care should be taken when cascading devices or channels to always read in the same channel order, as well as the byte order already mentioned. to freeze all three channels with a single read cycle (in cascaded or non-cascaded mode) the /kli-klon pins of all channels are connected with a pull-up resistor to v cc (see system application). this ensures that only one channel is operating as the ?master? and all others are ?slaves?. if an external ?freeze? of the positioning system is required, an external /kli-klo pulse will program all channels as slaves. this is derived by generating an external /kli-klo pulse before the first read cycle appears after system reset.
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 13/29 PE12316 pin description pin name pin number i/o description 68 plcc /cs 12 input chip select. a low enables the device. /rd 8 input read. when this and /cs are active (low), the data from the output register will be present on the data bus. d0 d1 d2 d3 d4 d5 d6 d7 14 15 17 18 20 21 23 24 input/ output lsb data bus buffer: 8-bit bi-directional buffer with 3-state outputs connected to the mi croprocessor system. msb /borrow1 /borrow2 /borrow3 58 56 54 output counter underflow signal. /carry1 /carry2 /carry3 59 57 54 output counter overflow signal. /kli-klo1 /kli-klo2 /kli-klo3 62 61 60 input/ output (od) cascade load input / cascade load output. open drain (od) output with internal 75kohm (nom) pull- up. external pull up required for full speed operation. /ready 63 output (od) when low signal indicates to the mpu that read or write may be completed. /ready falling edge synchronous with clk open drain output needs external pull-up. m21 m11 m01 m22 m12 m02 m23 m13 m03 29 28 27 34 32 30 37 36 35 input input input input input input input input input mode select inputs (see table 1 ) ua11 ua21 39 41 input input measuring input signals channel 1 (schmitt-trigger characteristics)
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 14/29 PE12316 pin description pin name pin number i/o description 68 plcc ua12 ua22 ua13 ua23 42 43 44 45 input input input input measuring input signals channel 2 (schmitt trigger characteristics) measuring input signals channel 3 (schmitt trigger characteristics) /ua01 /ua02 /ua03 3 2 1 input input input zero pulse for each channel. when active (low), the counter in the appropriate channel is cleared. other logic is not affected. (schmitt trigger characteristics) clk 68 input clock. used for internal synchronisation and control timing. (schmitt trigger characteristics) /a0 9 input byte select. a high level selects the least significant byte. a low level selects the most significant byte. /a1 /a2 10 11 input input channel select. see table 2 /a3 6 input selects bits 16- 23 of chosen channel. internal pullup. for details see table 3 memory map . /reset 5 input device reset. when active (low), the mode control logic is reset to a known state and the counter is cleared. (schmitt trigger characteristics) /we 7 input write enable. when /we and /cs are active (low), the data that is on the bus is loaded into the counter addressed by /a0, /a1, /a2 and /a3. /down1 /down2 /down3 47 49 51 input input input cascade input for counting down. /up1 /up2 /up3 46 48 50 input input input cascade input for counting up. v cc 16,22, 52,66 power supply voltage gnd 13,19, 25,53, 64 ground
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 15/29 PE12316 absolute maximum ratings over operating free air temperature: symbol parameter value units v cc dc supply voltage -0.3 to + 7.0 v v in dc input voltage -0.3 to v cc + 0.3 v i in dc input current +/- 10 ma storage temperature (plastic package) -40 to +125 c dc characteristics (referred to gnd): symbol parameter test condition min typ max units v oh all except, /ready and /kli-klo output high level i oh = -20 ua v cc -0.1 v v oh d0-d7 i oh = -8 ma, v cc = 5.0v 2.4 v v oh all except d0-d7, /ready and /kli-klo i oh = -6 ma, v cc = 3.3v 2.4 v v ol output low level i oh = 20 ua 0.1 v v ih input high level ttl schmitt trigger 2.0 2.4 v v il input low level 0.5 v i cc supply current 20 mhz v cc =max 25 ma vt+ schmitt trigger positive going threshold v cc = min to max 2.4 v vt- schmitt trigger negative going threshold v cc = min to max 0.5 v v hys schmitt trigger hysteresis v cc = min to max 0.2 v i oz tristate output leakage current v cc = max or gnd -10 +10 ua input high current -10 +10 ua i ih input with pullup v in = v cc -200 -10 ua i il input low current v in = gnd -10 +10 ua recommended operating conditions: symbol parameter value units v cc dc supply voltage 4.5 to 5.5 v v cc dc supply voltage (low power application) 3.0 to 3.6 v t ac temperature range 0 to +70 c
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 16/29 PE12316 timing requirements over reco mmended operating conditions symbol parameter min typ max units tc1 clk cycle time, duty cycle 50% 50 ns tc2 pulse width low clk 25 ns twrs pulse width, /reset input low 50 ns fmud maximum frequency, /upn or /downn, input duty cycle 50% 20 25 mhz twud pulse width, /upn or /downn input low 25 ns twk pulse width, /kli-klon input low 20 ns twrd1 pulse width, /rd input low (mode = 6 & 7) ns twrd2 pulse width, /rd input low (mode = 0 to 5) tc1 ns tdrd time between two read cycles (lsb and msb) 0 ns twwr pulse width, /we input low 25 ns tdwr time between two read cycles (lsb and msb) 0 ns tsd set up time, data prior to /we rising 15 ns tsus set up time, /cs and /rd low before clk falling edge 15 ns tsa set up time, /a0, /a1, /a2 prior to /we and /cs low 10 ns tsud set up time, /upn or /downn rising edge before clk falling edge 20 ns tsab set up time, ua1n or ua2n prior to clk falling edge. 15 ns tsda set up time, data prior to /we rising tsd ns tsbb set up time, ua2n stable before clk falling edge 15 ns tsac set up time, ua1 or ua2 rising edge before clk falling edge. 15 ns tsar set up time, /a0, /a1, /a 2 stable before /cs and /rd low after reset 10 ns tsbc set up time, ua1n or ua2n falling edge 15 ns tsr set up time, /reset high prior to clk falling edge. 0 ns tsuc set up time, /upn or /downn rising edge prior to /kli-klon (input) falling edge. 20 ns thdw hold time data after /we rising 10 ns twgp pulse width, ua1n input high (mode = 6) min 2 x tc1 ns twgp pulse width, ua2n input high (mode = 7) min 2 x tc1 ns tdgp pulse width, ua1n input low (mode = 6) min 2 x tc1 ns
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 17/29 PE12316 timing requirements over recommended operating conditions - continued symbol parameter min typ max units tdgf pulse width, ua2n input low (mode = 7) min 2 x tc1 ns tha address hold time after /we or /cs high 12 ns thab ua1n or ua2n hold time after clk falling edge 12 ns thda d0-d7 hold time after /a0 change 10 ns thac ua1n high hold time after clk falling edge 12 ns thbc ua2n hold time after clk falling edge 12 ns twrn pulse width, /ua0n input low 5 ns
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 18/29 PE12316 switching characteristics, (v cc = min, temperature +70 degrees) symbol parameter test conditions min typ max units tdd1 access time, /rd and clk to data output valid (mode = 0 to 5) 65 ns tdd2 access time, /rd to data output valid mode = 0 to 5 2 nd byte mode = 6-7 both bytes 45 ns thdr propagation delay /rd, /we or /cs inactive to /ready from cs 20 ns tdr propagation delay clk to /ready low 30 ns tduc propagation delay /upn or /downn rising edge to /carryn or /borrown rising edge from /upn to /carry 35 ns tdcc propagation delay from clk to /carryn or /borrown rising edge from /clk to /carry or from /clk to /borrow 25 ns tdco propagation delay clk falling edge to /kli-klon falling edge 55 ns tdcb propagation delay clk rising edge to /carryn or /borrown rising edge from /clk to /carry or /borrow 25 ns ted enable time /rd and /cs low to d0-d7 65 ns twco /kli-klon low output pulse width tc2 ns twcb /carryn or /borrown low output pulse width twud ns twcc /carryn or borrown low output pulse width tc2 ns thdr release time, data after /rd, /cs 0 45 ns
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 19/29 PE12316 figure 9 timing ? all modes figure 8 timing ?mode 1 - 5 figure 10 timing ? mode 6-7
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 20/29 PE12316 figure 11 read cycle
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 21/29 PE12316 figure 12 write cycle
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 22/29 PE12316 system application figure 13 shows a three axis microcomputer syste m using the PE12316. the clock of the microcomputer can be used to drive the PE12316 and addressing is either via memory mapped i/o or external i/o port addresses. the basic timing cycle must be chosen so that it matches that of the PE12316 read and write timing. in mode 0, a ll ua1n?s and ua2n?s must be connected to v cc . in all other modes /upn and /downn are tied to v cc . if a parallel freeze of all three channels is required all /kli-klon?s are connected together. one external pull-up (6.8k ? 12k) is required in this case. if the uaxn input are not used, they must be tied to v cc . figure 13 shows the mode 5 connection for quadruple count inputs of ua1n and ua2n. figure 13 three axis control system using PE12316 vcc 10k freeze reset clk wd rd d0...d7 a0...a15 cs 8-bit data bus 4 ua01 ua11 ua21 kli-klo1 ua02 ua12 ua22 kli-klo2 ua03 ua13 ua23 kli-klo3 clk m01 /02 /03 m21 /22 /23 m11 /12 /13 upn downn rd we reset cs d0...d7 a0-a3 axis 1 axis 2 axis 3 system- reset 8-bit micro- controller PE12316 address bus
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 23/29 PE12316 cascading to 32 bits figure 14 two cascaded channels (one 32-bit channel shown) in systems requiring a higher resolution, two PE12316?s or two channels of the PE12316 can be cascaded to achieve 32 bit accuracy figure 14 shows the block diagram of this application. it shows the two PE12316 devices with one channel of each cascaded to 32 bit. the ls-word PE12316 is operating in mode 5 and the ms-word in mode 0 (co unt only). the /kli-klo signals of each channel are connected together with a pull up of 10k and can be used as an external freeze input. in this case, the first external /kli-klo pul se, programming the PE12316 into t he slave mode, must occur before the first read cycle, otherwise the device channel re ceiving the first read cycle will be programmed into the master mode and generate a /kli-klo pulse for the second device. /up1 and /down1 of the first device are tied to vcc. both /ua01?s are connected together and can recover the zero pulse from the resolver. 4 4 10k 10k ua11 ua01 ua21 vcc cs clk d0...d7 a0?a3 we up1 down1 ua01 ua21 ua11 kli-klo m01 m11 m21 reset 1/3 PE12316 (ls-word) ready rd carry1 borrow1 cs clk d0...d7 a0?a3 we up2 down2 ua02 ua22 ua12 kli-klo m02 m12 m22 reset 1/3 PE12316 (ms-word) ready rd carry2 borrow2 car bor ready freeze reset cs 8 - bit data bus a0/1/2/3 rd wr clk d0...d7(msb)
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 24/29 PE12316 the system reset inputs of eac h PE12316 device (/reset) are conne cted together and must be used to ensure that the system is star ted from a known state after the power-up. if /ready is used from the PE12316, both are wired-or and a pull-up of 10k is connected to v cc to generate a proper high level in the non-active state (open drain output).
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 25/29 PE12316 plcc68 package dimensions package drawing: figure 15 plcc68 package dimension
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 26/29 PE12316 important notice productivity engineering gmbh (pe) reserves the right to make corrections, modi fications, enhancements, improvements, and other changes to it s products and services at any time and to discontinue any product or service without notice. customers should obtain the late st relevant information before placing orders and should verify that such information is current and complete. all pr oducts are sold subject to pe?s terms and conditions of sale supplied at the time of order acknowledgment. pe warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with pe?s standard warranty. testing and othe r quality control techniques are used to the extent pe deems necessary to support this warranty. except where mandated by government requi rements, testing of all parameters of each product is not necessarily performed. pe assumes no liability for applications assistance or cu stomer product design. customers are responsible for their products and applications using pe components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. pe does not warrant or represent that an y license, either express or implied, is granted under any pe patent right, copyright, mask work right, or other pe intellectual property right relating to any combination, machine, or process in which pe products or services are used. information published by pe regarding third?party products or services does not constitute a license from pe to use su ch products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or othe r intellectual property of the third party, or a license from pe under the patents or other intellectual property of pe. resale of pe products or services with statements different from or beyond the parameters stated by pe for that product or service voids all express and any implied warr anties for the associated pe product or service and is an unfair and deceptive business practice. pe is not responsible or liable for any such statements. mailing address: productivity engineering gmbh behringstr. 7 d-71083 herrenberg germany phone: (+49) 7032 / 2798-0 fax: (+49) 7032 / 2798-29 email: info@pe-gmbh.com
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 27/29 PE12316 application notes: 24 bit access to provide 24 bit counting on each channel, /a3 on pi n 6 is introduced. however it has to be kept in mind for cascading that /carry, /borrow are deriv ed from bits 0-15 of the counter to ensure compatibility with cf32006. the first channel in the chain can only be 16 bit wide to provide the correct interfacing signals carry/borrow to the following channel. however the last channel in the chain can use the full 24 bit. /a3 is located on pin 6 which is an "nc" pin on cf32006. this pin was not allowed to have a connection to the pcb board. therefore no compatibility issue should arise. as with all other addresslines, /a3 is low active. an internal pullup resistor ensures that /a3 can be left unconnected, if the 24 bit feature is not used. for details see table 3 memory map . possible cascading combinations: first channel second channel third channel resulting bitwidth 16 bit 16 bit none 32 bit 16 bit 24 bit none 40 bit 16 bit 16 bit 16 bit 48 bit 16 bit 16 bit 24 bit 56 bit table 5 cascading bitwidths read cycle: the readcycle is intended and designed synchronous to the clock. special care has to be taken for the parameter t sus ( the setup time of the falling edge of /rd before the falling clk edge). if t sus is not within spec, there is the possibility that the output register is not updated and the same value will be read twice. therefore the micropr ocessor system collecting the data and PE12316 should either have the same clock or the /rd on the PE12316 has to be synchronized into the PE12316 clock domain via an act74 type flipflop. electrical design recommendations: it is recommended that the PE12316 is used wit hout a socket and with at least 4 decoupling capacitors (100 nf) connected to vcc and gnd close to the package.
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 28/29 PE12316 figures figure 1 pinout ............................................................................................................................ 1 figure 2 block diagramm for 16 bit mode ................................................................................... 4 figure 3 direction discriminator modes ...................................................................................... 7 figure 4 direction discriminator up clock .................................................................................. 7 figure 5 direction discriminator down clock ............................................................................. 8 figure 6 pulse width measurement ............................................................................................. 9 figure 7 frequency measurement ............................................................................................. 10 figure 10 timing ? mode 6-7 ..................................................................................................... 19 figure 11 read cycle ................................................................................................................ 20 figure 12 write cycle ................................................................................................................ 21 figure 13 three axis control system using PE12316 ............................................................... 22 figure 14 two cascaded channels (one 32-bit channel shown) .............................................. 23 figure 15 plcc68 package dimension ..................................................................................... 25 tables table 1 mode description ............................................................................................................ 5 table 2 channel selection ........................................................................................................... 6 table 3 memory map ................................................................................................................... 6 table 4 mode selection ............................................................................................................. 11 table 5 cascading bitwidths ..................................................................................................... 27
PE12316 triple incremental encoder february 6, 2003 preliminary (version 1.1) february 6, 2003 (preliminary version 1.1) page 29/29 PE12316 contact information: for ordering and sample requests: adronic components gmbh bodelschwinghstr. 32 d-75031 eppingen germany phone: (+49) 7262 / 912360 fax: (+49) 7262 / 912361 email: info@adronic.de

▲Up To Search▲

Price & Availability of PE12316

	To Download PE12316 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .